Memory Cells And Arrays Of Elevationally-Extending Strings Of Memory Cells

ABSTRACT

A memory cell comprises channel material, insulative charge-passage material, programmable material, a control gate, and charge-blocking material between the programmable material and the control gate. The charge-blocking material comprises a non-ferroelectric insulator material and a ferroelectric insulator material comprising hafnium, zirconium, and oxygen. Other embodiments are disclosed.

RELATED PATENT DATA

This patent resulted from a continuation-in-part application of U.S. patent application Ser. No. 15/890,530, filed on Feb. 7, 2018, naming Haitao Liu, Kamal M. Karda, and Albert Fayrushin as inventors and entitled “Programmable Charge Storage Transistor, An Array Of Elevationally Extending Strings Of Memory Cells, And A Method Of Forming An Array Of Elevationally Extending Strings Of Memory Cells”, and which claims priority to U.S. Provisional Patent Application No. 62/610,846 filed on Dec. 27, 2017, the contents of which are hereby incorporated by reference.

TECHNICAL FIELD

Embodiments disclosed herein pertain to memory cells and to of elevationally-extending strings of memory cells.

BACKGROUND

Memory is one type of integrated circuitry and is used in computer systems for storing data. Memory may be fabricated in one or more arrays of individual memory cells. Memory cells may be written to, or read from, using digit lines (which may also be referred to as bitlines, data lines, or sense lines) and access lines (which may also be referred to as wordlines). The sense lines may conductively interconnect memory cells along columns of the array, and the access lines may conductively interconnect memory cells along rows of the array. Each memory cell may be uniquely addressed through the combination of a sense line and an access line.

Memory cells may be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods of time in the absence of power. Non-volatile memory is conventionally specified to be memory having a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed/rewritten to maintain data storage. Volatile memory may have a retention time of milliseconds or less. Regardless, memory cells are configured to retain or store memory in at least two different selectable states. In a binary system, the states are considered as either a “0” or a “1”. In other systems, at least some individual memory cells may be configured to store more than two levels or states of information.

A field effect transistor is one type of electronic component that may be used in a memory cell. These transistors comprise a pair of conductive source/drain regions having a semiconductive channel region there-between. A conductive gate is adjacent the channel region and separated there-from by a thin gate insulator. Application of a suitable voltage to the gate allows current to flow from one of the source/drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. Field effect transistors may also include additional structure, for example a reversibly programmable charge-storage region as part of the gate construction between the gate insulator and the conductive gate.

Flash memory is one type of memory and has numerous uses in modern computers and devices. For instance, modern personal computers may have BIOS stored on a flash memory chip. As another example, it is becoming increasingly common for computers and other devices to utilize flash memory in solid state drives to replace conventional hard drives. As yet another example, flash memory is popular in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized, and to provide the ability to remotely upgrade the devices for enhanced features.

NAND may be a basic architecture of integrated flash memory. A NAND cell unit comprises at least one selecting device coupled in series to a serial combination of memory cells (with the serial combination commonly being referred to as a NAND string). NAND architecture may be configured in a three-dimensional arrangement comprising vertically-stacked memory cells individually comprising a reversibly programmable vertical transistor. Control or other circuitry may be formed below the vertically-stacked memory cells. Other volatile or non-volatile memory array architectures may also comprise vertically-stacked memory cells that individually comprise a transistor

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagrammatic cross-sectional view of a memory cell in accordance with an embodiment of the invention.

FIG. 2 is a diagrammatic cross-sectional view of a memory cell in accordance with an embodiment of the invention.

FIG. 3 is a diagrammatic cross-sectional view of a memory cell in accordance with an embodiment of the invention.

FIG. 4 is a diagrammatic cross-sectional view of a memory cell in accordance with an embodiment of the invention.

FIG. 5 is a diagrammatic cross-sectional view of a memory cell in accordance with an embodiment of the invention.

FIG. 6 is a diagrammatic cross-sectional view of a memory cell in accordance with an embodiment of the invention.

FIG. 7 is a diagrammatic cross-sectional view of a portion of an array of elevationally-extending strings of memory cells in accordance with an embodiment of the invention.

FIG. 8 is a view taken through line 8-8 in FIG. 7.

FIG. 9 is a diagrammatic cross-sectional view of a portion of an array of elevationally-extending strings of memory cells in accordance with an embodiment of the invention.

FIG. 10 is a diagrammatic cross-sectional view of a portion of an array of elevationally-extending strings of memory cells in accordance with an embodiment of the invention.

FIG. 11 is a diagrammatic cross-sectional view of a portion of an array of elevationally-extending strings of memory cells in accordance with an embodiment of the invention.

FIG. 12 is a diagrammatic cross-sectional view of a memory cell in accordance with an embodiment of the invention.

FIG. 13 is a diagrammatic cross-sectional view of a memory cell in accordance with an embodiment of the invention.

FIG. 14 is a diagrammatic cross-sectional view of a memory cell in accordance with an embodiment of the invention.

FIG. 15 is a diagrammatic cross-sectional view of a portion of an array of elevationally-extending strings of memory cells in accordance with an embodiment of the invention.

FIG. 16 is a view taken through line 16-16 in FIG. 15.

FIG. 17 is a diagrammatic cross-sectional view of a memory cell in accordance with an embodiment of the invention.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Embodiments of the invention encompass memory cells and arrays of elevationally-extending strings of memory cells. A first example embodiment is shown in FIG. 1, which comprises a substrate or substrate fragment 100 having a base substrate 104 within and over which a memory cell 102 is shown. Base substrate 104 may comprise a semiconductor substrate. In this document, the term “semiconductor substrate” or “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. Base substrate 104 may be part of a larger substrate, for example a semiconductor wafer.

Transistor 102 comprises an example gate construction 101, example channel material 42, and example source/drain regions 103 and 105. Regions 103 and 105 and material 42 may comprise semiconductor material (e.g., silicon) having suitable conductivity-type and concentration of conductivity-modifying impurities therein to enable current to flow along example straight-line direction 31 of current flow in channel material 42 based upon selected operation of transistor gate construction 101. As examples, source/drain regions 103, 105 may be suitably conductively doped with conductivity-increasing dopant of one type and channel material 42 may doped to a lesser concentration with an impurity of another conductivity type. Additional regions may be included (not shown), for example LDD and/or halo regions.

Transistor gate construction 101 comprises insulative charge-passage material 40 (e.g., a bandgap-engineered structure having nitrogen-containing material such as silicon nitride sandwiched between two insulating oxides such as silicon dioxide), programmable material 34 (e.g., charge-storage material such as floating gate material such as doped or undoped silicon, or charge-trapping material such as silicon nitride, metal dots, etc.), a control gate 28 (e.g., comprising conductive control-gate material 22 such as elemental metals, metal material, and conductively-doped-semiconductive materials, including mixtures thereof), and charge-blocking material 32 between programmable material 34 and control gate 28. Charge-blocking material 32 comprises a non-ferroelectric insulator material 17 and a ferroelectric insulator material 15. In one embodiment and as shown, ferroelectric insulator material 15 and non-ferroelectric insulator material 17 are directly against one another, and in one embodiment ferroelectric insulator material 15 is thinner than non-ferroelectric insulator material 17. Regardless, an example thickness for ferroelectric insulator material 15 is 10 to 100 Angstroms, with 20 to 50 Angstroms being ideal. Example thicknesses for each of materials 40, 34 17, and 22 are 30 to 250 Angstroms. Example non-ferroelectric insulator materials are silicon dioxide and/or silicon nitride (e.g., silicon nitride sandwiched between two layers of silicon dioxide). Example ferroelectric insulators include metal oxide-comprising materials comprising one or more of transition metal oxide, zirconium, zirconium oxide, hafnium, hafnium oxide, lead zirconium titanate, tantalum oxide, strontium oxide, strontium titanium oxide, titanium oxide, and barium strontium titanate, and which may have dopant therein which comprises one or more of silicon, aluminum, lanthanum, yttrium, erbium, calcium, magnesium, strontium, lutetium, dysprosium, gadolinium, praseodymium, chromium, niobium, tantalum, hafnium, zirconium, vanadium manganese, cobalt, nickel, carbon and any other rare earth element. One particular example is a hafnium and zirconium-based oxide having suitable dopant therein. Other examples include a hafnium and silicon-based oxide having suitable dopant therein; a yttrium and zirconium based oxide having suitable dopant therein; and a hafnium, silicon, and zirconium based oxide.

In one embodiment, ferroelectric insulator material 15 comprises hafnium, zirconium, and oxygen. In one such embodiment, ferroelectric insulator material 15 comprises, consists of, or consists essentially of Hf_(x)Zr_(1-x)O₂ where x is from 0.3 to 0.7. In one embodiment, ferroelectric insulator material 15 comprises, consists of, or consists essentially of Hf_(x)Zr_(y)Q_(z)O₂ where:

-   -   x, y, and z are greater than 0;     -   x+y+z is no greater than 1.0;     -   y is greater than 0.7 or less than 0.3; and     -   Q is a material whose presence renders the ferroelectric         insulator material to be ferroelectric.         By way of example, Q may be any of the elemental dopants         referred to in the preceding paragraph. In one embodiment, y is         greater than 0.7. In one embodiment, y is less than 0.3. In one         embodiment, x+y+z is from 0.5 to 1.0, and in one such embodiment         is 1.0.

In one embodiment, non-ferroelectric insulator material 17 is closer to programmable material 34 then is ferroelectric insulator material 15, in one embodiment ferroelectric insulator material 15 is directly against control gate 28, and in one embodiment non-ferroelectric insulator material 17 is directly against programmable material 34. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

FIG. 2 shows an alternate example memory cell 102 a of a substrate 100 a comprising a gate construction 101 a having charge-blocking material 32 a. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix “a”. In construction 101 a, and in one embodiment, ferroelectric insulator material 15 is closer to programmable material 34 than is non-ferroelectric insulator material 17, in one embodiment non-ferroelectric insulator material 17 is directly against control gate 28, and in one embodiment ferroelectric insulator material 15 is directly against programmable material 34. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

FIG. 3 shows an alternate example memory cell 102 b of a substrate 100 b comprising a gate construction 101 b having charge-blocking material 32 b. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix “b” or with different numerals. Ferroelectric insulator material 15 in charge-blocking material 32 b is sandwiched between two regions 37, 39 of non-ferroelectric insulator material 17 along a direction that is parallel straight-line direction 31 of current flow in channel material 42. Example thicknesses for each of regions 37, 39 and material 15 is 10 to 100 Angstroms. In one embodiment and as shown, ferroelectric insulator material 15 is directly against non-ferroelectric insulator material 17 of each of two regions 37, 39. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

FIG. 4 shows an alternate example memory cell 102 c of a substrate 100 c comprising a gate construction 101 c having charge-blocking material 32 c. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix “c”. Non-ferroelectric insulator material 17 of charge-blocking material 32 c is sandwiched between two regions 37, 39 of ferroelectric insulator material 15 along a direction that is parallel straight-line direction 31 of current flow in channel material 42. In one embodiment and as shown, non-ferroelectric insulator material 17 is directly against ferroelectric insulator material 15 in each of two regions 37, 39. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

FIGS. 1-4 show example embodiments wherein ferroelectric insulator material 15 is continuous between edges 33, 35 of control gate 28 parallel straight-line direction 31 of current flow in channel material 42. Alternately, such ferroelectric insulator material may be discontinuous between those edges. Such an example embodiment is shown in FIG. 5 with respect to a memory cell 102 d of a substrate 100 d comprising a gate construction 101 d having charge-blocking material 32 d. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix “d”. Charge-blocking material 32 d is shown with ferroelectric insulator material 15 being discontinuous between edges 33, 35 of control gate 28 parallel straight-line direction 31 of current flow in channel material 42. Only two example spaced segments of ferroelectric insulator material 15 are shown, although more may be formed and variously positioned. In one embodiment and as shown, non-ferroelectric insulator material 17 is laterally between the discontinuous segments of ferroelectric insulator material 15. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

FIGS. 1-5 show examples wherein transistor 102/102 a/102 b/102 c/102 d is horizontal or within 10° of horizontal. Alternately, a memory cell may be fabricated to be elevationally-extending or other than elevationally-extending. FIG. 6 shows an example memory cell 102 e of a substrate 100 e that extends elevationally, with the particularly depicted embodiment transistor 102 e being vertical or within 10° of vertical. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix “e” or with different numerals. Channel material 42 e in the example embodiment of FIG. 6 is shown as being sandwiched between insulative charge-passage material 40 e and a backing dielectric material 50 (e.g., silicon dioxide and/or silicon nitride). Source/drain regions are not specifically shown in FIG. 6, for example as might occur with respect to an elevationally-extending string of memory cells wherein source/drain regions are provided at a top and a bottom of a stack of such memory cells, for example as will be described below. Dielectric material 27 (e.g., silicon dioxide and/or silicon nitride) is above and below gate construction 101 e. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

An embodiment of the invention comprises an array of elevationally-extending strings of memory cells, for example as shown in FIGS. 7 and 8. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix “f” or with different numerals. FIGS. 7 and 8 show a construction 10 that may comprise any one or more of conductive/conductor/conducting, semiconductive/semiconductor/semiconducting, or insulative/insulator/insulating (i.e., electrically herein) materials. Various materials have been formed elevationally over base substrate 104. Materials may be aside, elevationally inward, or elevationally outward of the FIGS. 7 and 8-depicted materials. For example, other partially or wholly fabricated components of integrated circuitry may be provided somewhere above, about, or within base substrate 11. Control and/or other peripheral circuitry for operating components within an array of components (e.g., of memory cells) may also be fabricated and may or may not be wholly or partially within an array or sub-array. Further, multiple sub-arrays may also be fabricated and operated independently, in tandem, or otherwise relative one another. In this document, a “sub-array” may also be considered as an array.

Construction 10 comprises an array 12 of elevationally-extending strings 44 of memory cells 30. Only a single string 44 is shown, although likely hundreds, thousands, tens of thousands, etc. of such strings will be in array 12. Approximate locations of memory cells 30 are indicated with brackets in FIG. 7 and with a dashed outline in FIG. 8, with memory cells 30 being essentially ring-like or annular in the depicted example. Array 12 comprises a vertical stack 16 of alternating insulative tiers 19 and conductive tiers 20. Example tiers 19 comprise insulative material 24, for example silicon dioxide. Example tiers 20 comprise conductive control-gate material 22 having terminal ends 26 corresponding to control-gate regions 28 of individual memory cells 30. Control-gate regions 28 may be part of individual control-gate lines 29 (only one being shown and numerically designated in FIG. 8) that interconnect multiple memory cells of multiple strings of memory cells within individual conductive tiers 20 in a row direction. Dielectric material 23 (FIG. 8; e.g., silicon dioxide and/or silicon nitride) is laterally between control-gate lines 29. Array 12 is shown as having seven vertically-alternating tiers 19, 20 in FIG. 7, although fewer or likely many more (e.g., dozens, hundreds etc.) may be formed. Accordingly, more tiers 19 and 20 may be above and/or below the depicted tiers. Tiers 19 and 20 may be of any suitable vertical thickness(es) and may have the same or different vertical thickness(es) relative one another. As an example, tiers 19 and 20 may have respective thicknesses of about 10 nanometers (nm) to 300 nm. Channel openings 13 extend through alternating tiers 19, 20, with only one channel opening 13 being shown with respect to a single elevationally-extending string 44 of memory cells 30.

Programmable material 34 f of individual memory cells 30 extends elevationally along individual control-gate regions 28. Charge-blocking material 32 f (i.e., a charge block) extends elevationally along individual control-gate regions 28 between programmable material 34 f and individual control-gate regions 28. Charge-blocking material 32 f comprises non-ferroelectric insulator material 17 and ferroelectric insulator material 15. Transistor channel material 42 f of individual memory cells 30 extends elevationally along programmable material 34 f. Insulative charge-passage material 40 f extends elevationally along programmable material 34 f between transistor channel material 42 f and programmable material 34 f. Example memory cell string 44 is shown as comprising radially-central solid dielectric material 50 (e.g., silicon nitride, spin-on-dielectric, and/or silicon dioxide). Alternately, and by way of example only, the radially-central portion of memory cell string 44 may include void space(s) (not shown) and/or be devoid of solid material (not shown).

A charge block may have the following functions in a memory cell: In a program mode, the charge block may prevent charge carriers from passing out of the programmable material (e.g., floating-gate material, charge-trapping material, etc.) toward the control gate, and in an erase mode the charge block may prevent charge carriers from flowing into the programmable material from the control gate. Accordingly, a charge block may function to block charge migration between the control-gate region and the programmable material of individual memory cells.

Alternate existing or yet-to-be developed constructions may be used. For example, multiple memory cells may be formed about a single string in an individual conductive tier 20, for example by bifurcating the FIG. 8-depicted control-gate line 29 longitudinally down its middle (not shown) thus creating two memory cells (not shown) that may be separately controlled if such bifurcated control-gate lines are separately controllable.

Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

FIGS. 7 and 8 show an example embodiment wherein ferroelectric insulator material 15 and non-ferroelectric insulator material 17 are each directly above and directly below programmable material 34 f in individual memory cells 30, and also where non-ferroelectric insulator material 17 is directly against a top 41 and a bottom 43 of programmable material 34 f in individual memory cells 30. An alternate embodiment example elevationally-extending string 44 of memory cells 30 is shown in FIG. 9. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix “g”. FIG. 9 also shows an embodiment wherein each of ferroelectric insulator material 15 and non-ferroelectric insulator material 17 is directly above and directly below programmable material 34 f in individual memory cells 30, but wherein ferroelectric insulator material 15 is directly against tops 41 and bottoms 43 of the programmable material. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

FIG. 10 shows an alternate example elevationally-extending string 44 h of memory cells 30 with respect to a construction 10 h. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix “h”. Ferroelectric insulator material 15 is neither directly above nor directly below programmable material 34 h in individual memory cells 30. Additionally, FIG. 10 shows an embodiment wherein non-ferroelectric insulator material 17 is neither directly above nor directly below programmable material 34 g in individual memory cells 30. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

Referring to FIG. 11, another alternate embodiment elevationally-extending string 44 j of memory cells 30 is shown with respect to a construction 10 j. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix “j”. Ferroelectric insulator material 15 of programmable material 34 f is directly above and directly below control-gate material 22 in individual memory cells 30, and in one embodiment is directly against a top 47 and a bottom 49 of control-gate material 22 in individual memory cells 30. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

As shown, the transistor channel material extends elevationally continuously along multiple of the insulative tiers and the conductive tiers (FIGS. 7-11). In one embodiment, the programmable material extends elevationally-along multiple of the insulative tiers and the conductive tiers (FIGS. 10 and 11). In another embodiment, the programmable material extends elevationally-along only individual ones of the conductive tiers and not elevationally-along the insulative tiers (FIGS. 7-9).

FIG. 12 shows another alternate embodiment memory cell 102 f of a substrate 100 f comprising a gate construction 101 f having charge-blocking material 32 f. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix “f” or with different numerals. In construction 101 f, metal material 55 is between non-ferroelectric insulator material 17 and ferroelectric insulator material 15. An example thickness for metal material 55 is no more than 3 nanometers, with from 1 nanometer to 2 nanometers being more preferred. Metal material 55 may effectively increase the degree/quanta of ferroelectricity of ferroelectric insulator material 15. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used. For example, and by way of examples only, FIGS. 13, 14, and 15/16 show alternate embodiment memory cells 102 g, 102 h, and 102 k, respectively, of substrates 100 g, 100 h, and 100 k, respectively, comprising gate constructions 101 g, 101 h, and 101 k,respectively, having charge-blocking materials 32 g, 32 h, and 32 k, respectively. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix “g”, “h”, or “k”, respectively. The constructions of FIGS. 13, 14, and 15/16 correspond to FIGS. 5, 6, and 7/8, respectively, and have metal materials 55 g, 55 h, and 55 k, respectively. Yet, and again, any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

FIG. 17 shows another alternate embodiment memory cell 102 m of a substrate 100 m comprising a gate construction 101 m having charge-blocking material 32 m. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix “m” or with different numerals. In construction 101 m, the ferroelectric insulator material comprises first and second different composition ferroelectric insulator materials 15 and 18, respectively, and non-ferroelectric insulator material 17 m. In one embodiment, the first and second different composition ferroelectric insulator materials are directly against one another. In one embodiment, the first and second different composition ferroelectric insulator materials each comprise hafnium, zirconium, and oxygen (e.g., but have at least one different molar concentration with respect to hafnium, zirconium, and oxygen). In another embodiment, one of the first and second different composition ferroelectric insulator materials does not comprise a combination of hafnium and zirconium. Ferroelectric insulator materials 15 and 18 may be of the same thickness or of different thicknesses relative one another and may be in different positions relative one another. Further, any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

Ferroelectric insulator material used as disclosed herein may exhibit negative capacitance whereby the transistor may exhibit favorable properties of low effective oxide thickness that may lead to faster programming and erase.

The above processing(s) or construction(s) may be considered as being relative to an array of components formed as or within a single stack or single deck of such components above or as part of an underlying base substrate (albeit, the single stack/deck may have multiple tiers). Control and/or other peripheral circuitry for operating or accessing such components within an array may also be formed anywhere as part of the finished construction, and in some embodiments may be under the array (e.g., CMOS under-array). Regardless, one or more additional such stack(s)/deck(s) may be provided or fabricated above and/or below that shown in the figures or described above. Further, the array(s) of components may be the same or different relative one another in different stacks/decks. Intervening structure may be provided between immediately-vertically-adjacent stacks/decks (e.g., additional circuitry and/or dielectric layers). Also, different stacks/decks may be electrically coupled relative one another. The multiple stacks/decks may be fabricated separately and sequentially (e.g., one atop another), or two or more stacks/decks may be fabricated at essentially the same time.

The assemblies and structures discussed above may be used in integrated circuits/circuitry and may be incorporated into electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic systems may be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

In this document unless otherwise indicated, “elevational”, “higher”, “upper”, “lower”, “top”, “atop”, “bottom”, “above”, “below”, “under”, “beneath”, “up”, and “down” are generally with reference to the vertical direction. “Horizontal” refers to a general direction (i.e., within 10 degrees) along a primary substrate surface and may be relative to which the substrate is processed during fabrication, and vertical is a direction generally orthogonal thereto. Reference to “exactly horizontal” is the direction along the primary substrate surface (i.e., no degrees there-from) and may be relative to which the substrate is processed during fabrication. Further, “vertical” and “horizontal” as used herein are generally perpendicular directions relative one another and independent of orientation of the substrate in three-dimensional space. Additionally, “elevationally-extending” and “extend(ing) elevationally” refer to a direction that is angled away by at least 45° from exactly horizontal. Further, “extend(ing) elevationally”, “elevationally-extending”, “extend(ing) horizontally”, “horizontally-extending” and the like with respect to a field effect transistor are with reference to orientation of the transistor's channel length along which current flows in operation between the source/drain regions. For bipolar junction transistors, “extend(ing) elevationally” “elevationally-extending”, “extend(ing) horizontally”, “horizontally-extending” and the like, are with reference to orientation of the base length along which current flows in operation between the emitter and collector. In some embodiments, any component, feature, and/or region that extends elevationally extends vertically or within 10° of vertical.

Further, “directly above”, “directly below”, and “directly under” require at least some lateral overlap (i.e., horizontally) of two stated regions/materials/components relative one another. Also, use of “above” not preceded by “directly” only requires that some portion of the stated region/material/component that is above the other be elevationally outward of the other (i.e., independent of whether there is any lateral overlap of the two stated regions/materials/components). Analogously, use of “below” and “under” not preceded by “directly” only requires that some portion of the stated region/material/component that is below/under the other be elevationally inward of the other (i.e., independent of whether there is any lateral overlap of the two stated regions/materials/components).

Any of the materials, regions, and structures described herein may be homogenous or non-homogenous, and regardless may be continuous or discontinuous over any material which such overlie. Where one or more example composition(s) is/are provided for any material, that material may comprise, consist essentially of, or consist of such one or more composition(s). Further, unless otherwise stated, each material may be formed using any suitable existing or future-developed technique, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implanting being examples.

Additionally, “thickness” by itself (no preceding directional adjective) is defined as the mean straight-line distance through a given material or region perpendicularly from a closest surface of an immediately-adjacent material of different composition or of an immediately-adjacent region. Additionally, the various materials or regions described herein may be of substantially constant thickness or of variable thicknesses. If of variable thickness, thickness refers to average thickness unless otherwise indicated, and such material or region will have some minimum thickness and some maximum thickness due to the thickness being variable. As used herein, “different composition” only requires those portions of two stated materials or regions that may be directly against one another to be chemically and/or physically different, for example if such materials or regions are not homogenous. If the two stated materials or regions are not directly against one another, “different composition” only requires that those portions of the two stated materials or regions that are closest to one another be chemically and/or physically different if such materials or regions are not homogenous. In this document, a material, region, or structure is “directly against” another when there is at least some physical touching contact of the stated materials, regions, or structures relative one another. In contrast, “over”, “on”, “adjacent”, “along”, and “against” not preceded by “directly” encompass “directly against” as well as construction where intervening material(s), region(s), or structure(s) result(s) in no physical touching contact of the stated materials, regions, or structures relative one another.

Herein, regions-materials-components are “electrically coupled” relative one another if in normal operation electric current is capable of continuously flowing from one to the other, and does so predominately by movement of subatomic positive and/or negative charges when such are sufficiently generated. Another electronic component may be between and electrically coupled to the regions-materials-components. In contrast, when regions-materials-components are referred to as being “directly electrically coupled”, no intervening electronic component (e.g., no diode, transistor, resistor, transducer, switch, fuse, etc.) is between the directly electrically coupled regions-materials-components.

The composition of any of the conductive/conductor/conducting materials herein may be metal material and/or conductively-doped semiconductive/semiconductor/semiconducting material. “Metal material” is any one or combination of an elemental metal, any mixture or alloy of two or more elemental metals, and any one or more conductive metal compound(s).

Herein, “selective” as to etch, etching, removing, removal, depositing, forming, and/or formation is such an act of one stated material relative to another stated material(s) so acted upon at a rate of at least 2:1 by volume. Further, selectively depositing, selectively growing, or selectively forming is depositing, growing, or forming one material relative to another stated material or materials at a rate of at least 2:1 by volume for at least the first 75 Angstroms of depositing, growing, or forming.

Unless otherwise indicated, use of “or” herein encompasses either and both.

CONCLUSION

In some embodiments, a memory cell comprises channel material, insulative charge-passage material, programmable material, a control gate, and charge-blocking material between the programmable material and the control gate. The charge-blocking material comprises a non-ferroelectric insulator material and a ferroelectric insulator material comprising hafnium, zirconium, and oxygen.

In some embodiments, a memory cell comprises channel material, insulative charge-passage material, programmable material, a control gate, and charge-blocking material between the programmable material and the control gate. The charge-blocking material comprises a non-ferroelectric insulator material, a ferroelectric insulator material, and metal material between the non-ferroelectric insulator material and the ferroelectric insulator material.

In some embodiments, a memory cell comprises channel material extending vertically or within 10° of vertical, insulative charge-passage material, programmable material, a control gate, and charge-blocking material between the programmable material and the control gate. The charge-blocking material comprises a non-ferroelectric insulator material and a ferroelectric insulator material comprising hafnium, zirconium, and oxygen. The ferroelectric insulator material and the non-ferroelectric insulator material are directly against one another. The ferroelectric insulator material is thinner than the non-ferroelectric insulator material.

In some embodiments, a memory cell comprises channel material extending vertically or within 10° of vertical, insulative charge-passage material, programmable material, a control gate, and charge-blocking material between the programmable material and the control gate. The charge-blocking material comprises a non-ferroelectric insulator material, a ferroelectric insulator material, and metal material between the non-ferroelectric insulator material and the ferroelectric insulator material. The ferroelectric insulator material is thinner than the non-ferroelectric insulator material.

In some embodiments, an array of elevationally-extending strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. The conductive tiers comprise control-gate material having terminal ends corresponding to control-gate regions of individual memory cells. Programmable material of the individual memory cells extends elevationally along individual of the control-gate regions. Charge-blocking material of the individual memory cells extends elevationally along the individual control-gate regions between the programmable material and the individual control-gate regions. The charge-blocking material comprises a non-ferroelectric insulator material and a ferroelectric insulator material comprising hafnium, zirconium, and oxygen. Transistor channel material of the individual memory cells extends elevationally along the programmable material and insulative charge-passage material extends elevationally along the programmable material between the transistor channel material and the programmable material.

in some embodiments, an array of elevationally-extending strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. The conductive tiers comprise control-gate material having terminal ends corresponding to control-gate regions of individual memory cells. Programmable material of the individual memory cells extends elevationally along individual of the control-gate regions. Charge-blocking material of the individual memory cells extends elevationally along the individual control-gate regions between the programmable material and the individual control-gate regions. The charge-blocking material comprises a non-ferroelectric insulator material, a ferroelectric insulator material, and metal material between the non-ferroelectric insulator material and the ferroelectric insulator material. Transistor channel material of the individual memory cells extends elevationally along the programmable material. Insulative charge-passage material extends elevationally along the programmable material between the transistor channel material and the programmable material.

In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the claims are not limited to the specific features shown and described, since the means herein disclosed comprise example embodiments. The claims are thus to be afforded full scope as literally worded, and to be appropriately interpreted in accordance with the doctrine of equivalents. 

1. A memory cell comprising: channel material; insulative charge-passage material; programmable material; a control gate; and charge-blocking material between the programmable material and the control gate, the charge-blocking material comprising: a non-ferroelectric insulator material; and a ferroelectric insulator material comprising hafnium, zirconium, and oxygen.
 2. The memory cell of claim 1 wherein the ferroelectric insulator material comprises Hf_(x)Zr_(1-x)O₂ where x is from 0.3 to 0.7.
 3. The memory cell of claim 1 wherein the ferroelectric insulator material consists of or consists essentially of Hf_(x)Zr_(1-x)O₂ where x is from 0.3 to 0.7.
 4. The memory cell of claim 1 wherein the ferroelectric insulator material comprises Hf_(x)Zr_(y)Q_(z)O₂ where: x, y, and z are greater than 0; x+y+z is no greater than 1.0; y is greater than 0.7 or less than 0.3; and Q is a material whose presence renders the ferroelectric insulator material to be ferroelectric.
 5. The memory cell of claim 4 wherein y is greater than 0.7.
 6. The memory cell of claim 4 wherein y is less than 0.3.
 7. The memory cell of claim 4 wherein x+y+z is from 0.5 to 1.0.
 8. The memory cell of claim 4 wherein x+y+z is 1.0.
 9. The memory cell of claim 1 wherein the ferroelectric insulator material consists of or consists essentially of Hf_(x)Zr_(y)Q_(z)O₂ where: x, y, and z are greater than 0; x+y+z is no greater than 1.0; y is greater than 0.7 or less than 0.3; and Q is a material whose presence renders the ferroelectric insulator material to be ferroelectric.
 10. The memory cell of claim 1 comprising metal material between the non-ferroelectric insulator material and the ferroelectric insulator material.
 11. The memory cell of claim 1 wherein the ferroelectric insulator material comprises first and second different composition ferroelectric insulator materials.
 12. The memory cell of claim 11 wherein the first and second different composition ferroelectric insulator materials are directly against one another.
 13. The memory cell of claim 11 wherein the first and second different composition ferroelectric insulator materials each comprise hafnium, zirconium, and oxygen.
 14. The memory cell of claim 11 wherein one of the first and second different composition ferroelectric insulator materials does not comprise a combination of hafnium and zirconium.
 15. The memory cell of claim 1 wherein the ferroelectric insulator material and the non-ferroelectric insulator material are directly against one another.
 16. The memory cell of claim 1 wherein the ferroelectric insulator material is thinner than the non-ferroelectric insulator material.
 17. The memory cell of claim 1 wherein the ferroelectric insulator material is continuous between edges of the control gate parallel a straight-line direction of current flow in the channel material.
 18. The memory cell of claim 1 wherein the ferroelectric insulator material is discontinuous between edges of the control gate parallel a straight-line direction of current flow in the channel material.
 19. The memory cell of claim 1 wherein the ferroelectric insulator material is closer to the programmable storage material than is the non-ferroelectric insulator material.
 20. The memory cell of claim 1 wherein the non-ferroelectric insulator material is closer to the programmable storage material than is the ferroelectric insulator material. 21-31. (canceled)
 32. A memory cell comprising: channel material; insulative charge-passage material; programmable material; a control gate; and charge-blocking material between the programmable material and the control gate, the charge-blocking material comprising: a non-ferroelectric insulator material; a ferroelectric insulator material; and metal material between the non-ferroelectric insulator material and the ferroelectric insulator material.
 33. (canceled)
 34. A memory cell comprising: channel material extending vertically or within 10° of vertical; insulative charge-passage material; programmable material; a control gate; and charge-blocking material between the programmable material and the control gate, the charge-blocking material comprising: a non-ferroelectric insulator material; a ferroelectric insulator material comprising hafnium, zirconium, and oxygen; and the ferroelectric insulator material and the non-ferroelectric insulator material being directly against one another, the ferroelectric insulator material being thinner than the non-ferroelectric insulator material.
 35. A memory cell comprising: channel material extending vertically or within 10° of vertical; insulative charge-passage material; programmable material; a control gate; and charge-blocking material between the programmable material and the control gate, the charge-blocking material comprising: a non-ferroelectric insulator material; a ferroelectric insulator material; metal material between the non-ferroelectric insulator material and the ferroelectric insulator material; and the ferroelectric insulator material being thinner than the non-ferroelectric insulator material.
 36. An array of elevationally-extending strings of memory cells, comprising: a stack comprising vertically-alternating insulative tiers and conductive tiers, the conductive tiers comprising control-gate material having terminal ends corresponding to control-gate regions of individual memory cells, programmable material of the individual memory cells extending elevationally along individual of the control-gate regions; charge-blocking material of the individual memory cells extending elevationally along the individual control-gate regions between the programmable material and the individual control-gate regions, the charge-blocking material comprising: a non-ferroelectric insulator material; and a ferroelectric insulator material comprising hafnium, zirconium, and oxygen; transistor channel material of the individual memory cells extending elevationally along the programmable material; and insulative charge-passage material extending elevationally along the programmable material between the transistor channel material and the programmable material. 37-46. (canceled)
 47. An array of elevationally-extending strings of memory cells, comprising: a stack comprising vertically-alternating insulative tiers and conductive tiers, the conductive tiers comprising control-gate material having terminal ends corresponding to control-gate regions of individual memory cells, programmable material of the individual memory cells extending elevationally along individual of the control-gate regions; charge-blocking material of the individual memory cells extending elevationally along the individual control-gate regions between the programmable material and the individual control-gate regions, the charge-blocking material comprising: a non-ferroelectric insulator material; a ferroelectric insulator material; and metal material between the non-ferroelectric insulator material and the ferroelectric insulator material; transistor channel material of the individual memory cells extending elevationally along the programmable material; and insulative charge-passage material extending elevationally along the programmable material between the transistor channel material and the programmable material. 